1. Field of the Invention
The present invention relates to a semiconductor memory device having an error correction circuit (hereinafter abbreviated as ECC) incorporated therein.
2. Description of the Related Art
Some semiconductor memory devices have error correction circuits incorporated therein for correcting errors, when errors are found in data during reading of the data from a memory cell array. An ECC generally has functions of (1) detecting whether there is an error bit in the data, (2) determining the position of the error bit, and (3) correcting the error bit, for data of any bit length. While the function (1) is capable of detecting errors in data of any bit length by adding 1-bit parity bits, implementing the function of (2) and (3) requires a plurality of the parity bits for data of any bit length.
In general, correction of 1-bit error in a 32-bit data requires 6 parity bits, correction of 1-bit error in a 16-bit code word requires 5 parity bits and correction of 1-bit error in a 8-bit code word requires 4 parity bits. As for the error size that can be corrected in one step of correction, 1-bit correction is commonly employed when the ECC is used in a semiconductor memory device, in consideration of the number of parity bits required.
A semiconductor memory device having the built-in ECC, particularly one applied to a so-called masked ROM (read-only memory) that allows only to read out data once the device has been manufactured, is disclosed in Japanese Patent Laid-open Publication No. Hei 5-20896. This semiconductor memory device of the prior art will be described below with reference to FIG. 1. FIG. 1 is a block diagram of a masked ROM having ECCs that are capable of correcting 1-bit errors included in the 8-bit data.
In FIG. 1, a memory cell array (C0-C7) 1 consists of memory cell transistors comprising a plurality of MOS transistors arranged in a matrix. A parity cell array (P0-P3) 2 consists of parity cell (ECC cell) transistors comprising a plurality of MOS transistors arranged in a matrix. An address buffer circuit (AB) 3 receives an address signal as an input from the outside and outputs this signal to a pre-decode circuit 4. Output of the pre-decode circuit (PD) 4 is input to Y select circuits (YC, YP) 5a, 5b and an X decoder circuit (X0) 6. The Y select circuit 5a is a selector for data cells (memory cells), and the Y select circuit 5b is a selector for ECC cells. The pre-decode circuit 4, the Y select circuits (YC, YP) 5a, 5b and the x decoder circuit (X0) 6 connect word select lines that pass channels of cell transistors in the memory call array (C0-C7) 1 and the parity cell array (P0-P3) 2 and DIGIT lines that connect to drains of cell transistors in the memory cell array (C0-C7) 1 and the parity cell array (P0-P3) 2 to sense amplifier circuits (S0-S7, E0-E3) 7, in accordance with a combination of internal address signals that are output from the address buffer circuit (AB) 3. The sense amplifier circuits (S0-S7, E0-E3) 7 detect information written on the memory call transistor and on the parity cell transistor that have been selected. An error detection circuit (ECC1) 8 and a syndrome decoder circuit (ECC2) 9 determine whether there is an error and locate an error bit, respectively, based on the information from the parity cell and the memory cell. Correction circuits (CR0.about.CR7) 10 correct the data of a bit indicated by a syndrome signal output from the syndrome decoder circuit (ECC2) 9. An output buffer circuit (OB) 11 delivers output data (SC0.about.SC7) of the correction circuits (CR0.about.CR7) 10 to an external system.
The address buffer circuit (AB) 3, the pre-decode circuit (PD) 4, the Y select circuits (YC, YP) 5a, 5b, the X decoder circuit (X0) 6, the sense amplifier circuits (S0-S6, E0-E3) 7 and the output buffer circuit (OB) 11 perform exactly the same functions as those of a semiconductor memory device commonly used, and description thereof will be omitted.
In the case of a masked ROM having a built-in ECC that is capable of correcting 1-bit error generated in 8-bit data, 8-bit memory cells in the memory cell array and 4-bit parity cells in the parity cell array are selected by the pre-decode circuit (PD), the Y select circuits (YC, YP) and the X decoder circuit (X0), so that 8-bit memory cell data and 4-bit parity cell data are read by the sense amplifier circuit.
"1" or "0" data are written in the memory cells and the parity cells by whether impurity ions are injected into the channel zone during diffusion or not. In case the memory cell transistors and the parity cell transistors are formed from NOR type N-channel transistors, P type ions (B ions or the like) are used as the impurity ions.
Description that follows assumes that the sense amplifier output is H (high) when the impurity ions are injected and is L (low) when the impurity ions are not injected.
In the case of a masked ROM, data to be written on the memory cell transistor is determined by a user of the masked ROM.
Data to be written in a parity cell, on the other hand, is determined by data of the memory cell transistor. When an address signal is input, for example, 8-bit data C00, C01, C02, C03, C04, C05, C06, C07 are output from the memory cells C0, C1, C2, C3, C4, C5, C6, C7 by the sense amplifier and, at the same time, P00, P01, P02, P03 are output from the parity cells P0, P1, P2, P3 that are selected by the address signals. At this time, data to be written in the parity cells P0, P1, P2, P3 are determined so that the following equation 1 (determinant) is satisfied. EQU H.multidot.Vt=0 (1)
where H; check matrix
V=[PO0 PO1 PO2 PO3 CO0 CO1 CO2 CO3 CO4 CO5 CO6 CO7] PA0 (1) To reduce the memory cell selecting time by decreasing the bit length of the word select line for memory cell selection, thereby to decrease the resistance and capacitance of the word select line. PA0 (2) To reduce the memory cell selecting time by decreasing the bit length of the DIGIT line for memory cell selection, thereby to decrease the resistance and capacitance of the DIGIT line.
While any of several check matrixes shown in FIG. 2 may used, the check matrix (1) in FIG. 2 will be employed in the description that follows.
Such a case will be taken as an example as 8-bit output data from the sense amplifier is (C00, C01, C02, C03, C04, C05, C06, C07)=(00101100). By substituting the 8-bit data and the check matrix (1) in FIG. 2 to the determinant shown in equation 1, the following equations 2 through 5 are obtained. EQU P00+C00+C01+C03+C04+C06=P00+0+0+0+1+0=0 (2) EQU P01+C00+C02+C03+C05+C06=P01+0+1+0+1+0=0 (3) EQU P02+C01+C02+C03+C07=P02+0+1+0+0=0 (4) EQU P03+C04+C05+C06+C07=P03+1+1+0+0=0 (5)
By calculating the above equations with mode 2 (binary), parity cell data of (P00, P01, P02, P03)=(1010) are obtained for the 8-bit data (C00, C01, C02, C03, C04, C05, C06, C07)=(00101100).
Logic circuits for the above equations (equations 2 through 5) are shown in FIG. 3. The circuits shown in FIG. 3 consist of XOR (exclusive logical sum) gates, and will be hereinafter called the error detection circuit. In FIG. 3, circuit group ECC 10 that includes XOR100, 101, 102, 103, 104 represents the equation 2, circuit group ECC 11 that includes XOR110, 111, 112, 113, 114 represents the equation 3, circuit group ECC 12 that includes XOR100, 121, 122, 123 represents the equation 4 and circuit group ECC 13 that includes XOR130, 131, 132, 133 represents the equation 5.
When there is no error in the data (P00, P01, P02, P03, C00, C01, C02, C03, C04, C05, C06, C07)=(101000101100) used as the example, outputs D0, D1, D2, D3 of the error detection circuit are all "0". When the memory cell or the parity cell has a fault and causes an error in the above data, on the other hand, either of the outputs D0, D1, D2, D3 of the error detection circuit is turned to "1". The outputs D0, D1, D2, D3 of the error detection circuit are called syndrome signals. In an ECC that carries out 1-bit error correction in the 8-bit data, a syndrome signal of 4-bit length is generated. The syndrome signal shows whether there is an error or not and the location of the error, when there is one. FIG. 4 shows the values of syndrome signals and the error bits indicated thereby. Correspondence between the values of syndrome signals and the error bits varies depending on the check matrix shown in FIG. 2. The correspondence shown in FIG. 4 is based on the check matrix (1) of FIG. 2.
A circuit that converts the syndrome signal of 4-bit length into an 8-bit signal that corresponds to the output bit length is called a syndrome decoder that is shown in FIG. 5. When there is an error in data C01, namely C01 has been changed from the correct value of "0" to "1", for example, the syndrome signals (D0, D1, D2, D3) become (1010) according to the table in FIG. 4, and the output (SY0, SY1, SY2, SY3, SY4, SY5, SY6, SY7) of the syndrome decoder circuit in response to the input of the syndrome signal is (01000000).
The output of the syndrome decoder circuit is input to the error correction circuit shown in FIG. 6. The error correction circuit shown in FIG. 6 consists of eight 2-input XOR (exclusive logical sum) gates that receive the output (C00, C01, C02, C03, C04, C05, C06, C07) of the sense amplifier and the output (SY0, SY1, SY2, SY3, SY4, SY5, SY6, SY7) of the syndrome decoder as the inputs. When one of the input terminals of the 2-input XOR gate receives "1" signal, the gate delivers an output that is an inversion of the another input and, when one of the inputs is "0", another input is output without inverting. As such, in case the data includes an error and the output of the syndrome decoder (SY0, SY1, SY2, SY3, SY4, SY5, SY6, SY7) includes a "1" bit, the error correction circuit gives an output that is the inversion of the output of the sense amplifier corresponding to the error bit. Since C01 has the error in this example, SY1 is set to "1", the error correction circuit outputs the inverted data of C01 as the output of SC1. Since all the syndrome decoder outputs other than SY1 are "0", all outputs of the error correction circuit except for SC1 are the same as the sense amplifier outputs.
As described above, even when the output of the sense amplifier circuit has changed to (C00, C01, C02, C03, C04, C05, C06, C07)=(01101100) for the true data of (C00, C01, C02, C03, C04, C05, C06, C07)=(00101100) because of an error in C01 due to defective memory cell or the like, the error correction circuit delivers output (SC0, SC1, SC2, SC3, SC4, SC5, SC6, SC7) of (00101100). Since the output (00101100) of the error correction circuit is identical with the true data (00101100), this means that error correction is successfully achieved.
In the semiconductor memory device having the ECC incorporated therein, however, since the final output is determined in the process through the error detection circuit, the syndrome decoder and the error correction circuit following the reading of the data from the memory cell by the sense amplifier as shown in FIG. 1, access speed of the device becomes slower than the case without the built-in ECC by the time of processing by four XOR gates, two INV gates and one NAND gate in the case of 1-bit correction in 8-bit data. Measurement of an access speed of ECC that corrects 1 bit in 64-bit data has shown that the difference in the access speed from a case without built-in ECC is about 10 ns.
In the development of an actual semiconductor memory device, in case the requirement for the processing speed cannot be satisfied due to the delay of about 10 ns in the access speed due to the ECC circuit, it is necessary to increase the processing speed of the circuits other than the ECC circuit because the number of steps of gates in the logical circuit or ECC cannot be decreased in the prior art configuration. In the case of a masked ROM, the access speed is most heavily affected by the charging time of the word select line and the charging time of the DIGIT line when selecting the memory cell. Therefore, the following measures may be employed for increasing the access speed.
In case the measures (1) and (2) are taken, however, number of divisions of the memory cell array increases that leads to increasing number of peripheral circuits such as XDEC and results in a greater chip size.